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Paper Defect Pretreatment System Based on FPGA
  
DOI：10.11980/j.issn.0254-508X.2013.08.010
Key Words:paper defect detection  field programmable gate array (FPGA)  hardware acceleration  image preprocessing  high-speed camera
Fund Project:陕西省科技统筹创新工程计划项目(2012KTCQ01-19)；陕西省科技攻关项目(2011K06-06)；陕西省教育厅专项科研计划项目(2010JK420)；陕西科技大学科研启动基金(BJ10-05)；陕西科技大学学术骨干培育计划(XSG2010010)。
Author NameAffiliation
刘　勇1 1.陕西科技大学电气与信息工程学院,陕西西安,710021 
周　强1 1.陕西科技大学电气与信息工程学院,陕西西安,710021 
刘　涛2 2.中国电子科技集团公司第29研究所,四川成都,610036 
杨雁南1 1.陕西科技大学电气与信息工程学院,陕西西安,710021 
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Abstract:In view of the bottleneck problem that the current computer serial data processing mode is hard to adapt to process the large amount of data in the online paper defect detection system, a paper defect detection hardware structure of “FPGA & computer” is applied. FPGA(Field Programmable Gate Array) can be used to achieve the hardware acceleration of image processing algorithm. First, paper image which was taken by high-speed CCD camera is preprocessed by FPGA. Secondly, the position and size of paper defects are preliminary determined. And then, these above information is sent to a computer through the Ethernet to further identification and classification. The results showed that this structure can greatly reduce computation volume, and improve the accuracy and efficiency of paper defect detection system.
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